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| SSM4532GM N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY D2 N-CH BVDSS RDS(ON) ID G2 S2 30V 50m 5A -30V 70m -4A Simple Drive Requirement Low On-resistance Fast Switching D2 D1 D1 P-CH BVDSS RDS(ON) ID SO-8 S1 G1 DESCRIPTION The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is universally preferred for all commercialindustrial surface mount applications and suited for low voltage applications such as DC/DC converters. D1 D2 Pb-free; RoHS-compliant G1 S1 G2 S2 ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 30 20 5 4 20 2.0 0.016 -55 to 150 -55 to 150 P-channel -30 20 -4 -3.2 -20 Units V V A A A W W/ Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-amb Parameter Thermal Resistance Junction-ambient 3 Value Max. 62.5 Unit /W 08/17/2007 Rev.1.00 www.SiliconStandard.com 1 SSM4532GM N-CH ELECTRICAL CHARACTERISTICS @Tj=25oC (unless otherwise specified) Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage 2 Test Conditions VGS=0V, ID=250uA Min. Typ. Max. Units 30 1 0.037 50 70 3 1 25 - V V/ m m V S uA uA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=1mA RDS(ON) Static Drain-Source On-Resistance VGS=10V, ID=5A VGS=4.5V, ID=4.2A 8 10.2 1.2 3.4 6 9 15 5.5 240 145 55 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=70 C) o VDS=VGS, ID=250uA VDS=10V, ID=5A VDS=30V, VGS=0V VDS=24V, VGS=0V VGS=20V ID=5A VDS=10V VGS=10V VDS=10V ID=1A RG=6,VGS=10V RD=10 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol IS VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=1.2V Tj=25, IS=1.7A, VGS=0V Min. Typ. Max. Units 1.7 1.2 A V Forward On Voltage 2 08/17/2007 Rev.1.00 www.SiliconStandard.com 2 SSM4532GM P-CH ELECTRICAL CHARACTERISTICS @Tj=25 C (unless otherwise specified) o Symbol BVDSS BVDSS/Tj Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=70 C) o o Test Conditions VGS=0V, ID=250uA 2 Min. Typ. Max. Units -30 -1 -0.028 70 90 -3 -1 -25 - V V/ m m V S uA uA nC nC nC ns ns ns ns pF pF pF Breakdown Voltage Temperature Coefficient Reference to 25, ID=-1mA RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss VGS=-10V, ID=-4A VGS=-4.5V, ID=-3A VDS=VGS, ID=-250uA VDS=-10V, ID=-4A VDS=-30V, VGS=0V VDS=-24V, VGS=0V VGS= 20V ID=-4A VDS=-10V VGS=-10V VDS=-10V ID=-1A RG=6,VGS=-10V RD=10 VGS=0V VDS=-25V f=1.0MHz 5 18.3 3.6 1.5 8 9 21 10 760 345 90 Gate-Source Leakage Total Gate Charge 2 100 nA Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol IS VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=-1.2V Tj=25, IS=-1.7A, VGS=0V Min. Typ. Max. Units -1.7 A -1.2 V Forward On Voltage 2 Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2 3.Surface mounted on 1 in copper pad of FR4 board ; 135/W when mounted on Min. copper pad. 08/17/2007 Rev.1.00 www.SiliconStandard.com 3 SSM4532GM N-Channel 70 50 T C =25 C 60 o T C =150 o C 10V 10V 40 50 8.0V ID , Drain Current (A) 30 8.0V ID , Drain Current (A) 40 6.0V 6.0V 20 30 20 4.0V 10 4.0V 10 V GS =3.0V V GS =3.0V 0 0 1 2 3 4 5 6 7 8 9 0 0 1 2 3 4 5 6 7 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 85 1.8 75 I D =5A T C =25 1.6 I D =5A V GS =10V RDS(ON) (m ) 65 Normalized RDS(ON) 3 4 5 6 7 8 9 10 11 1.4 1.2 55 1.0 45 0.8 35 0.6 -50 0 50 100 150 V GS (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 08/17/2007 Rev.1.00 www.SiliconStandard.com 4 SSM4532GM N-Channel 3 6 5 ID , Drain Current (A) 4 2 3 PD (W) 1 0 25 50 75 100 125 150 0 50 100 150 2 1 0 T c , Case Temperature ( C) o T c ,Case Temperature ( o C) Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation Case Temperature 100 1 Duty Factor = 0.5 Normalized Thermal Response (Rthja) 0.2 10 1ms 10ms 1 0.1 0.1 0.05 ID (A) 0.02 100ms 1s 0.1 0.01 P DM 0.01 t T Single Pulse T C =25 o C Single Pulse 0.01 0.1 1 10 10s DC Duty Factor = t/T Peak Tj = PDM x Rthja + Ta Rthja =135 oC/W 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 08/17/2007 Rev.1.00 www.SiliconStandard.com 5 SSM4532GM N-Channel f=1.0MHz 12 1000 10 VGS , Gate to Source Voltage (V) I D =5A V DS =10V Ciss 8 6 C (pF) Coss 100 Crss 4 2 0 0 2 4 6 8 10 12 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100 3 2.5 10 2 T j =150 o C IS(A) T j =25 o C 1 VGS(th) (V) 1.3 1.5 1.5 1 0.1 0.5 0.01 0.1 0.3 0.5 0.7 0.9 1.1 0 -50 0 50 100 150 V SD (V) T j ,Junction Temperature ( o C) Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage v.s. Junction Temperature 08/17/2007 Rev.1.00 www.SiliconStandard.com 6 SSM4532GM N-Channel VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.33x RATED VDS RG G + 10V - S VGS 10% VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE QG 10V D 0.33 x RATED VDS G S + QGS QGD VGS 1~ 3 mA I G I D Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform 08/17/2007 Rev.1.00 www.SiliconStandard.com 7 SSM4532GM P-Channel 20 20 -10V -8.0V -6.0V 15 -10V -8.0V -6.0V 15 -ID , Drain Current (A) V GS =-4.0V 10 -ID , Drain Current (A) V GS =-4.0V 10 5 5 T C =25 o C 0 0 1 2 3 4 T C =150 o C 0 0 1 2 3 4 5 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 90 1.8 I D =-4.0A 80 I D =-4.0A T C =25 1.6 V GS = -10V Normalized RDS(ON) 70 1.4 RDS(ON) (m ) 60 1.2 50 1 40 0.8 30 3 4 5 6 7 8 9 10 11 0.6 -50 0 50 100 150 -V GS (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 08/17/2007 Rev.1.00 www.SiliconStandard.com 8 SSM4532GM P-Channel 5 3 2.5 4 -ID , Drain Current (A) 2 3 PD (W) 2 1 0 25 50 75 100 125 150 1.5 1 0.5 0 0 50 100 150 T c , Case Temperature ( o C) T c ,Case Temperature ( o C) Fig 5. Maximum Drain Current v.s. Fig 6. Typical Power Dissipation Case Temperature 100 1 Duty Factor = 0.5 10 Normalized Thermal Response (R thja) 0.2 1ms -ID (A) 10ms 1 0.1 0.1 0.05 0.02 100ms 1s T C =25 o C Single Pluse 0.01 0.1 1 10 100 0.01 PDM 0.01 Single Pulse t T Duty Factor = t/T Peak Tj = P DM x Rthja+ Ta Rthja=135 oC/W 0.1 10s DC 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS (V) t , Pulse Width (s) Fig 7. Maximum Safe Operating Area Fig 8. Effective Transient Thermal Impedance 08/17/2007 Rev.1.00 www.SiliconStandard.com 9 SSM4532GM P-Channel 12 10000 f=1.0MHz 10 -VGS , Gate to Source Voltage (V) I D =-4A V DS =-10V 8 1000 Ciss Coss 6 4 C (pF) 100 Crss 2 0 0 2 4 6 8 10 12 14 16 18 20 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS (V) Fig 9. Gate Charge Characteristics Fig 10. Typical Capacitance Characteristics 100 3 2.5 10 T j =150 o C 2 -IS(A) T j =25 o C 1 -VGS(th) (V) 1.5 1 0.1 0.5 0.01 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0 -50 0 50 100 150 -V SD (V) T j ,Junction Temperature ( o C) Fig 11. Forward Characteristic of Reverse Diode Fig 12. Gate Threshold Voltage v.s. Junction Temperature 08/17/2007 Rev.1.00 www.SiliconStandard.com 10 SSM4532GM P-Channel VDS RD 90% D VDS TO THE OSCILLOSCOPE 0.33 x RATED VDS RG G 10% S -10 V VGS VGS td(on) tr td(off) tf Fig 13. Switching Time Circuit Fig 14. Switching Time Waveform VG VDS TO THE OSCILLOSCOPE QG -10V D G S -1~-3mA I G 0.33 x RATED VDS QGS QGD VGS ID Charge Q Fig 15. Gate Charge Circuit Fig 16. Gate Charge Waveform 08/17/2007 Rev.1.00 www.SiliconStandard.com 11 SSM4532GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 08/17/2007 Rev.1.00 www.SiliconStandard.com 12 |
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